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| programming:asm:huc6280_instruction_set [2020/05/09 16:59] – [Transfer X Register to Accumulator (TXA)] turboxray | programming:asm:huc6280_instruction_set [2020/07/25 05:18] (current) – ↷ Page moved from programming:programming:asm:huc6280_instruction_set to programming:asm:huc6280_instruction_set arkhan |
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| //* The following is an automated conversion of an excellent document originally available here: [[http://shu.emuunlim.com/download/pcedocs/pce_cpu.html]]// | //* The following is a conversion of the document (with corrections) originally available here: [[http://shu.emuunlim.com/download/pcedocs/pce_cpu.html]]// |
| ===== The HuC6280 CPU ===== | ===== The HuC6280 CPU ===== |
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| The PC-Engine uses a special version of the well-known 6502 CPU, apparently mimicking Rockwell's 65C02S variant. It has additional Opcodes, more addressing-modes, and a memory management unit (MMU). Page boundary penalties does not exist on the HuC6280, but it's speculated that it is automatically calculated for some instructions, as some are +1 over non-penalty 6502 versions. This is a list of Opcodes, that are available with the HuC6280 CPU. | The PC-Engine uses a special version of the well-known 6502 CPU, apparently mimicking Rockwell's 65C02S variant. It has additional Opcodes, more addressing-modes, and a memory management unit (MMU). Page boundary penalties does not exist on the HuC6280, but it's speculated that it is automatically calculated for some instructions, as some are +1 over non-penalty 6502 versions. This is a list of Opcodes, that are available with the HuC6280 CPU. Any instructions that read/write from the hardware bank $ff for address range $000 to $7ff have a +1 cycle penalty, +2 if it's a read-modify-write instruction (TSB, TRB). ST0/ST1/ST2 instruction already have the +1 cycle penalty included in their listing, so no need to add it. |
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| ===== Add With Carry (ADC) ===== | ===== Add With Carry (ADC) ===== |
