The PC-Engine uses a special version of the well-known 6502 CPU, apparently mimicking Rockwell's 65C02S variant. It has additional Opcodes, more addressing-modes, and a memory management unit (MMU). Page boundary penalties does not exist on the HuC6280, but it's speculated that it is automatically calculated for some instructions, as some are +1 over non-penalty 6502 versions. This is a list of Opcodes, that are available with the HuC6280 CPU.

Function Add the data located at the effective address specified by the operand to the contents of the accumulator. Add one to the result if the carry flag is set, and store the final result in the accumulator. This opcode takes one extra cycle to complete if the decimal mode flag D is set.

Adressing Modes & Opcodes

Flags Affected

Function Bitwise logical AND the data located at the effective address specified by the operand with the contents of the accumulator. Each bit in the accumulator is ANDed with the corresponding bit in memory, with the result being stored in the respective accumulator bit.

Adressing Modes & Opcodes

Flags Affected

Function Shift the contents of the location specified by the operand left one bit. That is, bit one takes on the value originally found in bit zero, bit two takes the value originally in bit one, and so on; bit 7 is transferred into the carry flag; bit 0 is cleared. The arithmetic result of the operation is an unsigned multiplication by two.

Adressing Modes & Opcodes

Flags Affected

Function The i th bit value in zero page memory location ZZ is tested. If it is clear, a branch is taken; if it is set, the instruction immediately following the three-byte BBRi instruction is executed. If the branch is taken, a one-byte signed displacement, fetched from the third byte of the instruction, is added to the program counter. Once the branch address has been calculated, the result is loaded into the program counter, transferring control to that location. The allowable range of the displacement is -128 to +127 from the instruction immediately following the branch. Add +2 cycles if branch is taken.

Adressing Modes & Opcodes

Flags Affected

Function The carry flag in the status register is tested. If it is clear, a branch is taken; if it is set, the instruction immediately following the two-byte BCC instruction is executed. If the branch is taken, a one-byte signed displacement, fetched from the third byte of the instruction, is added to the program counter. Once the branch address has been calculated, the result is loaded into the program counter, transferring control to that location. The allowable range of the displacement is -128 to +127 from the instruction immediately following the branch . Note that BCC determines if the result of a comparison is less than; therefore, BCC is sometimes written as BLT (Branch if Less Than). Add +2 cycles if branch is taken.

Adressing Modes & Opcodes

Flags Affected

Function The i th bit value in zero page memory location ZZ is tested. If it is set, a branch is taken; if it is clear, the instruction immediately following the three-byte BBSi instruction is executed. If the branch is taken, a one-byte signed displacement, fetched from the third byte of the instruction, is added to the program counter. Once the branch address has been calculated, the result is loaded into the program counter, transferring control to that location. The allowable range of the displacement is -128 to +127 from the instruction immediately following the branch. Add +2 cycles if branch is taken.

Adressing Modes & Opcodes

Flags Affected

Function The carry flag in the status register is tested. If it is set, a branch is taken; if it is clear, the instruction immediately following the two-byte BCS instruction is executed. If the branch is taken, a one-byte signed displacement, fetched from the third byte of the instruction, is added to the program counter. Once the branch address has been calculated, the result is loaded into the program counter, transferring control to that location. The allowable range of the displacement is -128 to +127 from the instruction immediately following the branch . Note that BCC determines if the result of a comparison is greater than or equal to; therefore, BCC is sometimes written as BGE (Branch if Greater than or Equal). Add +2 cycles if branch is taken.

Adressing Modes & Opcodes

Flags Affected

Function The zero flag in the status register is tested. If it is set, meaning that the last value tested (which affected the zero flag) was zero, a branch is taken; if it is clear, meaning the value tested was non-zero, the instruction immediately following the two-byte BEQ instruction is executed. If the branch is taken, a one-byte signed displacement, fetched from the third byte of the instruction, is added to the program counter. Once the branch address has been calculated, the result is loaded into the program counter, transferring control to that location. The allowable range of the displacement is -128 to +127 from the instruction immediately following the branch. Add +2 cycles if branch is taken.

Adressing Modes & Opcodes

Flags Affected

Function BIT sets the status register flags based on the result of two different operations. First, it sets or clears the N flag to reflect the value of the high bit (bit 7) of the data located at the effective address specified by the operand, and sets or clears the V flag to reflect the contents of the next-to-highest bit (bit 6) of the data addressed. Second, it logically ANDs the data located at the effective address with the contents of the accumulator; it changes neither value, but sets the Z flag if the result is zero, or clears it if the result is non-zero.

Adressing Modes & Opcodes

Flags Affected

Function The negative flag in the status register is tested. If it is set, meaning the high bit of the value which most recently affected the N flag was set, a branch is taken. Since numbers are often stored in two's complement, this instruction can be used to detect negative numbers. If it is clear, the instruction immediately following the two-byte BMI instruction is executed. If the branch is taken, a one-byte signed displacement, fetched from the third byte of the instruction, is added to the program counter. Once the branch address has been calculated, the result is loaded into the program counter, transferring control to that location. The allowable range of the displacement is -128 to +127 from the instruction immediately following the branch. Add +2 cycles if branch is taken.

Adressing Modes & Opcodes

Flags Affected

Function The zero flag in the status register is tested. If it is clear, meaning that the last value tested (which affected the zero flag) was zero, a branch is taken; if it is set, meaning the value tested was non-zero, the instruction immediately following the two-byte BNE instruction is executed. If the branch is taken, a one-byte signed displacement, fetched from the third byte of the instruction, is added to the program counter. Once the branch address has been calculated, the result is loaded into the program counter, transferring control to that location. The allowable range of the displacement is -128 to +127 from the instruction immediately following the branch. Add +2 cycles if branch is taken.

Adressing Modes & Opcodes

Flags Affected

Function The negative flag in the status register is tested. If it is clear, meaning the high bit of the value which most recently affected the N flag was cleared, a branch is taken. Since numbers are often stored in two's complement, this instruction can be used to detect positive numbers. If it is set, the instruction immediately following the two-byte BPL instruction is executed. If the branch is taken, a one-byte signed displacement, fetched from the third byte of the instruction, is added to the program counter. Once the branch address has been calculated, the result is loaded into the program counter, transferring control to that location. The allowable range of the displacement is -128 to +127 from the instruction immediately following the branch . This opcode takes one extra cycle if the branch is taken, and another extra cycle if a page boundary is crossed in taking the branch.

Adressing Modes & Opcodes

Flags Affected

Function A branch is always taken; no testing is done. A one-byte signed displacement, fetched from the third byte of the instruction, is added to the program counter. Once the branch address has been calculated, the result is loaded into the program counter, transferring control to that location. The allowable range of the displacement is -128 to +127 from the instruction immediately following the branch.

Adressing Modes & Opcodes

Flags Affected

Function Forces a software interrupt. BRK is unaffected by the I interrupt disable flag. Although BRK is a one-byte instruction, the program counter (which is pushed onto the stack by the instruction) is incremented by two; this lets you follow the break instruction with a one-byte signature byte indicating which break caused the interrupt. Be sure to pad BRK with a single byte to allow an RTI (return from interrupt) instruction to execute correctly. Multiple actions are invoked on a BRK. The program counter is incremented by 2. The high and low bytes of the program counter are pushed onto the stack in order, followed by the status register (P). The program counter is then loaded with the break vector stored at absolute address \$00FFF6-\$00FFF7. (Remember, the high byte is stored in \$00FFF7 and the low byte is stored in \$00FFF6.) The decimal flag D is cleared, and the I flag is set (to disable hardware IRQ interrupts) after a break is executed. Additionally, the break flag B in the status register value pushed onto the stack is set.

Adressing Modes & Opcodes

Flags Affected

Function Similar to the Jump to Subroutine (JSR) instruction, Branch to Subroutine allows execution of a subroutine. However, the offset is specified in relative mode instead of as an absolute address. This saves a byte, but takes one more clock cycle than JSR, so its use is discouraged. The current program counter is pushed onto the stack. A one-byte signed displacement, fetched from the second byte of the instruction, is added to the program counter. Once the subroutine address has been calculated, the result is loaded into the program counter, transferring control to that location. The allowable range of the displacement is -128 to +127 from the instruction immediately following the BSR.

Adressing Modes & Opcodes

Flags Affected

Function The overflow flag V in the status register is tested. If it is set, a branch is taken; if it is clear, the instruction immediately following the two-byte BVS instruction is executed. If the branch is taken, a one-byte signed displacement, fetched from the third byte of the instruction, is added to the program counter. Once the branch address has been calculated, the result is loaded into the program counter, transferring control to that location. The allowable range of the displacement is -128 to +127 from the instruction immediately following the branch . BVS is almost exclusively used to check that a two's complement arithmetic calculation has overflowed. Add +2 cycles if branch is taken.

Adressing Modes & Opcodes

Flags Affected

Function The overflow flag V in the status register is tested. If it is clear, a branch is taken; if it is set, the instruction immediately following the two-byte BVC instruction is executed. If the branch is taken, a one-byte signed displacement, fetched from the third byte of the instruction, is added to the program counter. Once the branch address has been calculated, the result is loaded into the program counter, transferring control to that location. The allowable range of the displacement is -128 to +127 from the instruction immediately following the branch . BVC is almost exclusively used to check that a two's complement arithmetic calculation has not overflowed. Add +2 cycles if branch is taken.

Adressing Modes & Opcodes

Flags Affected

Function The carry flag C in the status register is set to 0.

Adressing Modes & Opcodes

Flags Affected

Function The accumulator is set to \$#00.

Adressing Modes & Opcodes

Flags Affected

Function The decimal flag D in the status register is set to 0, returning the processor to binary arithmetic mode.

Adressing Modes & Opcodes

Flags Affected

Function The interrupt disable flag I in the status register is set to 0. This re-enables hardware interrupt (IRQ) processing.

Adressing Modes & Opcodes

Flags Affected

Function The overflow flag V in the status register is set to 0.

Adressing Modes & Opcodes

Flags Affected

Function The Y register is set to #\$00.

Adressing Modes & Opcodes

Flags Affected

Function The X register is set to #\$00.

Adressing Modes & Opcodes

Flags Affected

Function Subtract the data located at the effective address specified by the operand from the contents of the X register, setting the carry, zero, and negative flags based on the result, but without altering the contents of either the memory location or the accumulator. The comparison is of unsigned binary values only (decimal mode is ignored), and the result is not saved.

Adressing Modes & Opcodes

Flags Affected

Function Sets the HuC6280 to “high speed,” or normal speed mode. Used for switching the processor back into high-speed mode.

Adressing Modes & Opcodes

Flags Affected

Function Sets the HuC6280 to low speed. Need for accessing slow memory. The CD bios routines, and some hucards, use this for accessing BRAM.

Adressing Modes & Opcodes

Flags Affected

Function Subtract the data located at the effective address specified by the operand from the contents of the accumulator, setting the carry, zero, and negative flags based on the result, but without altering the contents of either the memory location or the accumulator. The comparison is of unsigned binary values only (decimal mode is ignored), and the result is not saved.

Adressing Modes & Opcodes

Flags Affected

Function Decrement by one the contents of the X register (subtract one from the value). DEX neither affects nor is affected by the carry flag.

Adressing Modes & Opcodes

Flags Affected

Function Decrement by one the contents of the location specified by the operand (subtract one from the value). DEC neither affects nor is affected by the carry flag.

Adressing Modes & Opcodes

Flags Affected

Function Subtract the data located at the effective address specified by the operand from the contents of the Y register, setting the carry, zero, and negative flags based on the result, but without altering the contents of either the memory location or the accumulator. The comparison is of unsigned binary values only (decimal mode is ignored), and the result is not saved.

Adressing Modes & Opcodes

Flags Affected

Function Bitwise logical Exclusive OR (XOR) the data located at the effective address specified by the operand with the contents of the accumulator. Each bit in the accumulator is XORed with the corresponding bit in memory, with the result being stored in the respective accumulator bit.

Adressing Modes & Opcodes

Flags Affected

Function Increments contents of the location specified by the operand (add one to the value). INC neither affects nor is affected by the carry flag.

Adressing Modes & Opcodes

Flags Affected

Function Increment by one contents of the X register (add one to the value). INX neither affects nor is affected by the carry flag.

Adressing Modes & Opcodes

Flags Affected

Function Decrement by one the contents of the Y register (subtract one from the value). DEY neither affects nor is affected by the carry flag.

Adressing Modes & Opcodes

Flags Affected

Function Increment by one contents of the Y register (add one to the value). INY neither affects nor is affected by the carry flag.

Adressing Modes & Opcodes

Flags Affected

Function Transfer control to the address specified by the operand field. The program counter is loaded with the target address.

Adressing Modes & Opcodes

Flags Affected

Function Transfer control to the subroutine at the location specified by the operand, after first pushing the current program counter value onto the stack as a return address. The value of the PC which is pushed onto the stack is the location of the last (third) byte of the JSR instruction, not the address of the next opcode.

Adressing Modes & Opcodes

Flags Affected

Function Load the accumulator with the data located at the effective address specified by the operand.

Adressing Modes & Opcodes

Flags Affected

Function Load the X register with the data located at the effective address specified by the operand.

Adressing Modes & Opcodes

Flags Affected

Function Load the Y register with the data located at the effective address specified by the operand.

Adressing Modes & Opcodes

Flags Affected

Function Logical shift the contents of the location specified by the operand right one bit. That is, bit zero takes on the value originally found in bit one, bit one takes the value originally in bit two, and so on; bit 7 is cleared; bit 0 is transferred into the carry flag. The arithmetic result of the operation is an unsigned division by two.

Adressing Modes & Opcodes

Flags Affected

Function Bitwise logical OR the data located at the effective address specified by the operand with the contents of the accumulator. Each bit in the accumulator is ORed with the corresponding bit in memory, with the result being stored in the respective accumulator bit.

Adressing Modes & Opcodes

Flags Affected

Function NOP performs no action, and is often used for timing loops or temporarily removing certain instructions.

Adressing Modes & Opcodes

Flags Affected

Function Push the accumulator onto the stack.

Adressing Modes & Opcodes

Flags Affected

Function Push the process status register P onto the stack.

Adressing Modes & Opcodes

Flags Affected

Function Push the X register onto the stack.

Adressing Modes & Opcodes

Flags Affected

Function Push the Y register onto the stack.

Adressing Modes & Opcodes

Flags Affected

Function Pull the value on the top of the stack into the accumulator. The previous contents of the accumulator are destroyed.

Adressing Modes & Opcodes

Flags Affected

Function Pull the value on the top of the stack into the processor status register P. The previous contents of the status register are destroyed.

Adressing Modes & Opcodes

Flags Affected

Function Pull the value on the top of the stack into the X register. The previous contents of the X register are destroyed.

Adressing Modes & Opcodes

Flags Affected

Function Pull the value on the top of the stack into the Y register. The previous contents of the Y register are destroyed.

Adressing Modes & Opcodes

Flags Affected

Function Rotate the contents of the location specified by the operand left one bit. That is, bit one takes on the value originally found in bit zero, bit two takes the value originally in bit one, and so on; bit 0 takes on the value in the carry flag; bit 7 is transferred into the carry.

Adressing Modes & Opcodes

Flags Affected

Function Clear the specified bit in the zero page memory location specified in the operand. The bit to clear is specified by a number concatenated to the end of the mnemonic, resulting in 8 distinct Opcodes.

Adressing Modes & Opcodes

Flags Affected

Function Rotate the contents of the location specified by the operand right one bit. That is, bit zero takes on the value originally found in bit one, bit one takes the value originally in bit two, and so on; bit 7 takes on the value in the carry flag; bit 0 is transferred into the carry.

Adressing Modes & Opcodes

Flags Affected

Function Pull the status register and the program counter from the stack in order. Normally used to return from an interrupt call (such as BRK), this instruction can also be used to pull the status register P, and the program counter low and high bytes from the stack into the P and program counter registers.

Adressing Modes & Opcodes

Flags Affected

Function Pull the program counter from the stack, incrementing the 16-bit value by one before loading the program counter with it. The low byte of the program counter is pulled from the stack first, followed by the high byte.

Adressing Modes & Opcodes

Flags Affected

Function The values of the accumulator and the X Register are swapped.

Adressing Modes & Opcodes

Flags Affected

Function The values of the accumulator and the Y Register are swapped.

Adressing Modes & Opcodes

Flags Affected

Function Subtract the data located at the effective address specified by the operand to the contents of the accumulator. Subtract one more from the result if the carry flag is set, and store the final result in the accumulator. This opcode takes one extra cycle if the decimal mode flag D is set.

Adressing Modes & Opcodes

Flags Affected

Function The decimal mode flag D in the status register is set to 1. This enables BCD arithmetic. Interrupt calls will save this setting, but clear it for inside the ISR. V flag is not affected for operations that work under Decimal mode.

Adressing Modes & Opcodes

Flags Affected

Function The carry flag C in the status register is set to 1.

Adressing Modes & Opcodes

Flags Affected

Function The interrupt disable flag I in the status register is set to 1. This disables hardware interrupt processing.

Adressing Modes & Opcodes

Flags Affected

Function The T flag in the status register is set to 1. The T flag is called the “Memory Operation Flag;”, when this flag is set all the instructions that normally use the A register act differently, I don't know exactly if all the instructions are affected but I'm sure for AND, EOR, OR & ADC. In place of using the A register the instruction use the memory location in ZP pointed by the X register, so for example if you use SET followed by ADC #10, the CPU will do ZP[X] = ZP[X] + 10. When the T flag is set, operations that work under the T flag will have a Read-Modify-Write +1 penalty.

Adressing Modes & Opcodes

Flags Affected

Function The immediate argument is stored in the HuC6270's address register. This command is equivalent to storing the immediate argument in \$1FE000. The HuC6270 “No. 0” register is also known as the HuC6270 Address/Status Register; more information is available in the HuC6270 summary. According to the Develo Book , this operation sets /CE7, A1, and A0 to logical LOW.

Adressing Modes & Opcodes

Flags Affected

Function The immediate argument is stored in the HuC6270's low data register. This command is equivalent to storing the immediate argument in \$1FE002. The HuC6270 “No. 1” register is also known as the HuC6270 Low Data Register; more information is available in the HuC6270 summary. According to the Develo Book , this operation sets /CE7 and A0 to logical LOW, while setting A1 to logical HIGH.

Adressing Modes & Opcodes

Flags Affected

Function The immediate argument is stored in the HuC6270's high data register. This command is equivalent to storing the immediate argument in \$1FE003. The HuC6270 “No. 2” register is also known as the HuC6270 High Data Register; more information is available in the HuC6270 summary. According to the Develo Book , this operation sets /CE7 to logical LOW, while setting A0 and A1 to logical HIGH.

Adressing Modes & Opcodes

Flags Affected

Function Set the specified bit in the zero page memory location specified in the operand. The bit to clear is specified by a number concatenated to the end of the mnemonic, resulting in 8 distinct Opcodes.

Adressing Modes & Opcodes

Flags Affected

Function Stores the value in the accumulator to the effective address specified by the operand.

Adressing Modes & Opcodes

Flags Affected

Function Store the value in the X register to the effective address specified by the operand.

Adressing Modes & Opcodes

Flags Affected

Function Store the value in the Y register to the effective address specified by the operand.

Adressing Modes & Opcodes

Flags Affected

Function Store the value #\$00 to the effective address specified by the operand. Very useful for initialising memory.

Adressing Modes & Opcodes

Flags Affected

Function Execute a memory move where the source address alternates between two addresses, and the destination address increments with each loop cycle. This is an extremely powerful instruction, mainly used for transferring data from the special video memory (e.g., backgrounds, etc.) to the main memory.

Adressing Modes & Opcodes

Flags Affected

Function Swaps the values stored in the X and Y registers.

Adressing Modes & Opcodes

Flags Affected

Function Loads Memory Mapping Register i with the value in the accumulator. More about the MPR registers can be found in the Memory Mapping summary. It is possible to load more than one MPR at a time by setting more than one bit in the immediate argument to TAM.

Adressing Modes & Opcodes

Flags Affected

Function Transfer the value in the accumulator to register X.

Adressing Modes & Opcodes

Flags Affected

Function Transfer the value in the accumulator to register Y.

Adressing Modes & Opcodes

Flags Affected

Function Execute a memory move where the source address increments, and the destination address alternates between two addresses with each loop cycle. This is an extremely powerful instruction, mainly used for transferring data to the special video memory (e.g., backgrounds, etc.) from the main memory.

Adressing Modes & Opcodes

Flags Affected

Function Execute a memory move where the source and destination addresses decrement with each loop cycle. This is an extremely powerful instruction, mainly used for copying and moving data around in main memory.

Adressing Modes & Opcodes

Flags Affected

Function Execute a memory move where the source address increments with each loop cycle. This is an extremely powerful instruction, mainly used for transferring data from the special video memory (e.g., backgrounds, etc.) to the main memory.

Adressing Modes & Opcodes

Flags Affected

Function Execute a memory move where the source and destination addresses increment with each loop cycle. This is an extremely powerful instruction, mainly used for copying and moving blocks of data around in main memory.

Adressing Modes & Opcodes

Flags Affected

Function Transfers the value in Memory Mapping Register i to the accumulator. More information about the MPRs can be found on the Memory Mapping summary. Only one bit in the immediate argument can be set to 1.

Adressing Modes & Opcodes

Flags Affected

Function Logically AND together the complement of the value in the accumulator with the data at the effective address specified by the operand. Store the result at the memory location. This clears each bit for which the corresponding accumulator bit is set, making it an ideal opcode for masking data. N and V and Z are set as in the BIT opcode instruction. These flags are set based on the ANDing of the uncomplemented accumulator value with the memory value.

Adressing Modes & Opcodes

Flags Affected

Function Logically OR together the value in the accumulator with the data at the effective address specified by the operand. Store the result at the memory location. This sets each bit for which the corresponding accumulator bit is set, making it an ideal opcode for masking data. N and V and Z are set as in the BIT opcode instruction. These flags are set based on the ANDing of the accumulator value with the memory value.

Adressing Modes & Opcodes

Flags Affected

Function Logically AND together the immediate operand with the data at the effective address specified by the operand. This sets each bit for which the corresponding immediate argument bit is set, making it an ideal opcode for masking data. N and V and Z are set as in the BIT opcode instruction.

Adressing Modes & Opcodes

Flags Affected

Function Transfer the value in the stack pointer S to the X register. The value of the stack pointer is not changed.

Adressing Modes & Opcodes

Flags Affected

Function Transfer the value in the X register to the accumulator. The value of the X register is not changed.

Adressing Modes & Opcodes

Flags Affected

Function Transfer the value in the Y register to the accumulator. The value of the Y register is not changed.

Adressing Modes & Opcodes

Flags Affected

Function Transfer the value in the X register to the stack pointer. The value of the X register is not changed.

Adressing Modes & Opcodes

Flags Affected